Recently, an active matrix display, in which a thin film transistor as an active element is integrated in each pixel, has come into widespread use. For example, in a mobile device, such as mobile phone, an active matrix liquid crystal display device, employing a polysilicon transistor, has come to be used widely because the display device may be of a reduced size.
Polysilicon thin film transistors are higher in mobility than amorphous silicon thin film transistors. Hence, a driving circuit, for example, may be fabricated by the same process as that for producing a pixel transistor that forms a pixel.
The driving circuit used in a display device includes a gate line driving circuit which drives a plurality of scanning lines (gate lines) and a source line driving circuit which drives a plurality of signal lines (source lines). The gate lines and the signal lines intersect each other. Each of the driving circuits includes a scanning circuit including a plurality of shift register stages.
In a shift register stage making up the scanning circuit, a CMOS (Complementary MOS) circuit, which is a combination of an n-channel transistor and a p-channel transistor, is generally used. However, in the CMOS manufacturing process, since both of a n-channel transistor and a p-channel transistor are to be manufactured, not only the number of process steps but also the manufacturing cost is increased.
To avoid these difficulties, such a driving circuit, composed only of p-channel transistors or n-channel transistors, that is, transistors of single conductivity types, has also been proposed.
The driving circuit, composed only of transistors of a single conductivity type, includes a shift register which makes use of a two-phase to four-phase clock signal. Each shift register stage is formed by a circuit exploiting a bootstrap effect.
As a related art of a shift register stage, making use of two-phase clocks, reference may be made to Patent Document 1 (JP Patent Kokai Publication No. JP-P2003-016794A). This shift register circuit includes n-number shift register stages RS(1) to RS(n), as shown herein in FIG. 16 (FIG. 4 of Patent Document 1). The shift register stage RS(k) includes an input signal terminal IN, an output signal terminal OUT, a reference voltage terminal SS, a constant voltage terminal DD, a clock signal input terminal clk (clk1 or clk2) and a reset signal input terminal RST. To the input signal terminal IN of the shift register stage RS(1) is supplied a start signal Vst from a controller. The input signal terminal IN of the stage RS(k) (k=2 to n) is connected to the output signal terminal OUT of the preceding stage RS(k−1). The reset signal input terminal RST of the stage RS(k) other than the last stage RS(n) is connected to the output signal terminal OUT of the succeeding stage RS(k+1). A reset signal Vrst from the controller is supplied to the reset signal input terminal RST of the last stage RS(n). A clock signal CK1 from the controller is supplied to the clock signal terminal clk1 of the odd stage RS(k), while a clock signal CK2 from the controller is supplied to the clock signal terminal clk2 of the even stage RS(k). The clocks CK1 and CK2 are alternately set to HIGH, every time slot, for a preset interval of each time slot during which an output signal of each shift register stage is shifted from one stage to the next. When a two-phase clock signal is used, an output of a succeeding stage shift register is used as a reset signal. Since there is no succeeding stage for the last stage, it is necessary to apply a devoted reset signal from outside for the last stage.
FIG. 17 (FIG. 10 of Patent Document 1) shows a configuration of a shift register stage disclosed in Patent Document 1. When an input signal is HIGH, transistors 21 and 34 are turned on, while the transistor 22 is turned off to raise the potential at a node A. If the input signal then goes LOW, the potential at the node A is maintained. If the clock signal clk1 goes HIGH, the potential at the node A is further raised, owing to a bootstrap effect, and hence a HIGH output signal OUT is output from the stage. When a reset signal RST is HIGH, the transistor 33 is turned on to set a node F to HIGH. The transistor 22 then is turned on to lower the potential at the node A. The on-state of transistor 22 is maintained until the input signal subsequently goes HIGH.
As a related art employing a three-phase clock signal, reference is made to Patent Document 2 (JP Patent Kokai Publication No. JP-P2003-346492A), for example. If a three-phase clock signal is used, the reset signal for the last stage, needed for the two-phase clock, no longer needs to be used. The same applies for a four-phase clock signal as well.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2003-016794A (see e.g., FIGS. 4, 10 and 11)    [Patent Document 2] JP Patent Kokai Publication No. JP-P2003-346492A (see e.g., FIG. 4)